Manufacturing method of semiconductor device

ABSTRACT

In MOSFET having SBD as a protection element, a TiW (alloy having tungsten as a main component) film is used as an aluminum-diffusion barrier metal film below an aluminum source electrode in order to secure properties of SBD. The present inventors have found that a tungsten-based barrier metal film is in the form of columnar grains having a lower barrier property than that of a titanium-based barrier metal film such as TiN so that aluminum spikes are generated relatively easily in a silicon substrate. In the present invention, when a tungsten-based barrier metal film is formed by sputtering as a barrier metal layer between an aluminum-based metal layer and a silicon-based semiconductor layer therebelow, the lower layer is formed by ionization sputtering while applying a bias to the wafer side and the upper layer is formed by sputtering without applying a bias to the wafer side.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a continuation of U.S. patent application Ser. No.12/727,337, filed on Mar. 10, 2010, which claims priority to JapanesePatent Application No. 2009-119641 filed on May 18, 2009, the disclosureof which, including the specification, drawings and abstract, isincorporated herein by reference in its entirety.

BACKGROUND OF THE INVENTION

The present invention relates to a technology effective when applied toa metal film forming technology in a manufacturing method of asemiconductor device (or a semiconductor integrated circuit device).

Japanese Patent Laid-Open No. 2004-247559 (Patent Document 1) and U.S.Patent Publication No. 2007-0148896 (Patent Document 2) disclose atechnology of forming a ruthenium film as a lower electrode of DRAM(dynamic random access memory) by sputtering according to a PCM (pointcusp magnetron) system (i.e., PCM sputtering) and CVD (Chemical VaporDeposition).

Japanese Patent Laid-Open No. 2004-358091 (Patent Document 3) and U.S.Patent Publication No. 2002-0089027 (Patent Document 4) disclose atechnology of forming, by a kind of ionization sputtering, a titaniumfilm, a titanium nitride film, or the like as a barrier metal layer foreffectively filling a contact hole with aluminum.

Japanese Patent Laid-Open No. 2001-127005 (Patent Document 5) disclosesa technology of forming a titanium film as a barrier metal film bysputtering based on an IMP (Ion Metal Plasma) system in order to fillaluminum in a hole with a high aspect ratio.

Japanese Patent Laid-Open No. 2000-223708 (Patent Document 6), JapanesePatent Laid-Open No. 2007-165663 (Patent Document 7), Japanese PatentLaid-Open No. 2001-267569 (Patent Document 8), and Japanese PatentLaid-Open No. 2006-32598 (Patent Document 9) disclose a technology ofusing TiW as a barrier metal of an aluminum source electrode of a trenchgate power MOSFET (metal oxide semiconductor field effect transistor).

Japanese Patent Laid-Open No. 223752/1998 (Patent Document 10), JapanesePatent Laid-Open No. 45281/1994 (Patent Document 11), and JapanesePatent Laid-Open No. 2000-21880 (Patent Document 12) disclose atechnology of forming a titanium film, a titanium nitride film (or TiW),or the like as a barrier metal layer of an aluminum interconnect byusing typical sputtering.

Japanese Patent Laid-Open No. 2003-318395 (Patent Document 13), U.S.Patent Publication 2003-0199156 (Patent Document 14), and U.S. PatentPublication 2005-0145899 (Patent Document 15) disclose a technology ofusing TiW as a barrier metal of an aluminum source electrode of a powerMOSFET and forming an aluminum source electrode by reflow.

-   [Patent Document 1] Japanese Patent Laid-Open No. 2004-247559-   [Patent Document 2] U.S. Patent Publication 2007-0148896-   [Patent Document 3] Japanese Patent Laid-Open No. 2001-358091-   [Patent Document 4] U.S. Patent Publication 2002-0089027-   [Patent Document 5] Japanese Patent Laid-Open No. 2001-127005-   [Patent Document 6] Japanese Patent Laid-Open No. 2000-223708-   [Patent Document 7] Japanese Patent Laid-Open No. 2007-165663-   [Patent Document 8] Japanese Patent Laid-Open No. 2001-267569-   [Patent Document 9] Japanese Patent Laid-Open No. 2006-32598-   [Patent Document 10] Japanese Patent Laid-Open No. 223752/1998-   [Patent Document 11] Japanese Patent Laid-Open No. 45281/1994-   [Patent Document 12] Japanese Patent Laid-Open No. 2000-21880-   [Patent Document 13] Japanese Patent Laid-Open No. 2003-318395-   [Patent Document 14] U.S. Patent Publication 2003-0199156-   [Patent Document 15] U.S. Patent Publication 2005-0145899

SUMMARY OF THE INVENTION

In MOSFET having a SBD (Schottky barrier diode) as a protection element,a TiW (an alloy comprised mainly of tungsten) film is used as analuminum diffusion barrier metal film below an aluminum source electrodein order to secure the properties of the SBD. The investigation by thepresent inventors has, however, revealed that compared with atitanium-based barrier metal film such as TiN, a tungsten-based barriermetal film is in the form of columnar grains inferior in barrierproperty so that aluminum spikes occur in a silicon substrate relativelyeasily.

The invention has been made with a view to overcoming theabove-described problem.

An object of the invention is to provide a high reliabilitymanufacturing process of a semiconductor device.

The above-described and the other objects and novel features of theinvention will be apparent from the description herein and accompanyingdrawings.

Of the inventions disclosed herein, typical ones will be describedbriefly as follows.

According to one mode of the present application, when a tungsten-basedbarrier metal film is formed by sputtering as a barrier metal layerbetween an aluminum-based metal layer and a silicon-based semiconductorlayer, the lower layer of it is formed by carrying out ionizationsputtering while applying a bias to the wafer side and the upper layerof it is formed by sputtering without applying a bias to the wafer side.

Typical advantages, among advantages available by the inventiondisclosed herein, will next be described briefly.

When a tungsten-based barrier metal film is formed by sputtering as abarrier metal layer between an aluminum-based metal layer and asilicon-based semiconductor layer lying therebelow, the lower layer ofit is formed by ionization sputtering while applying a bias to the waferside and the upper layer of it is formed by sputtering withoutsubstantially applying a bias to the wafer side. This enables to yield atungsten-based barrier metal film whose lower portion is in an amorphousform superior in barrier property.

BRIEF DESCRIPTION OF DRAWINGS

FIG. 1 is a plan view illustrating the configuration of a multi-chambertype wafer processing apparatus to be used for a manufacturing method ofa semiconductor device according to one embodiment of the presentapplication;

FIG. 2 is a schematic cross-sectional view of a PCM (point cuspmagnetron) system sputtering chamber to be used in a step of forming atungsten-based barrier metal film in the manufacturing method of asemiconductor device according to the one embodiment of the presentapplication;

FIG. 3 is a top view of a device illustrating one example of a powerMOSFET manufactured by the manufacturing method of a semiconductordevice according to the one embodiment of the present application;

FIG. 4 is a device cross-sectional flow diagram (a step of forming aresist pattern for the formation of a source contact trench) at a trenchgate cell portion in the manufacturing method of a semiconductor deviceaccording to the one embodiment of the present application;

FIG. 5 is a device cross-sectional flow diagram (a source/contact trenchformation step) at the trench gate cell portion in the manufacturingmethod of a semiconductor device according to the one embodiment of thepresent application;

FIG. 6 is a device cross-sectional flow diagram (a resist patternremoval step for forming the source/contact trench) at the trench gatecell portion in the manufacturing method of a semiconductor deviceaccording to the one embodiment of the present application;

FIG. 7 is a device cross-sectional flow diagram (a source/contact trenchextending step) at the trench gate cell portion in the manufacturingmethod of a semiconductor device according to the one embodiment of thepresent application;

FIG. 8 is a device top view (a p+ body/contact region introducing step)at the trench gate cell portion in the manufacturing method of asemiconductor device according to the one embodiment of the presentapplication;

FIG. 9 is a device cross-sectional flow diagram (the p+ body/contactregion introducing step) at the trench gate cell portion (correspondingto the X-X′ cross-section of FIG. 8) in the manufacturing method of asemiconductor device according to the one embodiment of the presentapplication;

FIG. 10 is a device top view (a formation step of a two-stage structureof a contact trench) at the trench gate cell portion in themanufacturing method of a semiconductor device according to the oneembodiment of the present application;

FIG. 11 is a device cross-sectional flow diagram (the formation step ofa two-stage structure of a contact trench) at the trench gate cellportion (corresponding to the X-X′ cross-section of FIG. 10) in themanufacturing method of a semiconductor device according to the oneembodiment of the present application;

FIG. 12 is a device cross-sectional flow diagram (a step of forming alower-layer barrier metal film) at the trench gate cell portion in themanufacturing method of a semiconductor device according to the oneembodiment of the present application;

FIG. 13 is a device cross-sectional flow diagram (the step of forming anupper-layer barrier metal film) at the trench gate cell portion in themanufacturing method of a semiconductor device according to the oneembodiment of the present application;

FIG. 14 is a device cross-sectional flow diagram (an aluminum-basedmetal film formation step) at the trench gate cell portion in themanufacturing method of a semiconductor device according to the oneembodiment of the present application;

FIG. 15 is a device cross-sectional flow diagram (a barrier metal filmformation step) at a trench gate cell portion in a manufacturing methodof a semiconductor device according to another embodiment of the presentapplication;

FIG. 16 is an extended cross-sectional structure view of the devicecorresponding to FIG. 14;

FIG. 17 is an equivalent circuit diagram of the device corresponding toFIG. 16; and

FIG. 18 is an SEM (scanning electron microscope) photographcorresponding to FIG. 13.

DETAILED DESCRIPTION OF THE INVENTION

[Outline of embodiment] First, typical embodiments of the inventiondisclosed herein are outlined.

1. A manufacturing method of a semiconductor device including thefollowing steps: (a) forming a recess downwards from the upper surfaceof a first insulating film over a first main surface of a semiconductorwafer; (b) forming a tungsten-based barrier metal film over the innersurface of the recess and the upper surface of the first insulatingfilm; (c) after the step (b), forming an aluminum-based metal layer tocover therewith the tungsten-based barrier metal film over the innersurface of the recess and the upper surface of the first insulatingfilm; wherein the step (b) includes the following sub-steps: (b1)forming a first-layer film of the tungsten-based barrier metal film overthe inner surface of the recess and the upper surface of the firstinsulating film by ionization sputtering while applying a bias voltageto the semiconductor wafer; and (b2) forming a second-layer film of thetungsten-based barrier metal film over the first layer film bysputtering without substantially applying a bias voltage to thesemiconductor wafer.

2. The manufacturing method of a semiconductor device as described abovein 1, wherein in the step (b), the tungsten-based barrier metal filmcontains tungsten as a main component thereof and titanium as asecondary component.

3. The manufacturing method of a semiconductor device as described abovein 1 or 2, wherein the first-layer film has mainly an amorphousstructure.

4. The manufacturing method of a semiconductor device as described abovein any one of 1 to 3, wherein the second-layer film has mainly acolumnar crystal structure.

5. The manufacturing method of a semiconductor device as described abovein any one of 1 to 4, wherein the sub-steps (b1) and (b2) are performedin a same film forming chamber.

6. The manufacturing method of a semiconductor device as described abovein any one of 1 to 4, wherein the sub-steps (b1) and (b2) are performedin film forming chambers different from each other.

7. The manufacturing method of a semiconductor device as described abovein any one of 1 to 6, wherein the sub-step (b2) is carried out withoutsubstantially applying a radio frequency bias voltage to a sputtertarget.

8. The manufacturing method of a semiconductor device as described abovein any one of 1 to 7, wherein the semiconductor wafer has, over thefirst main surface thereof, a number of semiconductor chip regions and aSchottky barrier diode is formed in each of the chip regions.

9. The manufacturing method of a semiconductor device as described abovein 8, wherein a power MOSFET is formed in each of the chip regions.

10. The manufacturing method of a semiconductor device as describedabove in any one of 1 to 9, wherein the recess has a two-stagestructure.

11. A manufacturing method of a semiconductor device including thefollowing steps: (a) forming a recess downwards from the upper surfaceof a first insulating film over a first main surface of a semiconductorwafer; (b) forming a tungsten-based barrier metal film over the innersurface of the recess and the upper surface of the first insulating filmby ionization sputtering while applying a bias voltage to thesemiconductor wafer; and (c) after the step (b), forming analuminum-based metal layer to cover therewith the tungsten-based barriermetal film over the inner surface of the recess and the upper surface ofthe first insulating film.

12. The manufacturing method of a semiconductor device as describedabove in 11, wherein in the step (b), the tungsten-based barrier metalfilm contains tungsten as a main component thereof and titanium as asecondary component.

13. The manufacturing method of a semiconductor device as describedabove in 11, wherein the tungsten-based barrier metal film has a layerhaving mainly an amorphous structure.

14. The manufacturing method of a semiconductor device as describedabove in 11 or 12, wherein the semiconductor wafer has, over the firstmain surface thereof, a number of semiconductor chip regions and aSchottky barrier diode is formed in each of the chip regions.

15. The manufacturing method of a semiconductor device as describedabove in 14, wherein a power MOSFET is formed in each of the chipregions.

16. The manufacturing method of a semiconductor device as describedabove in any one of 11 to 15, wherein the recess has a two-stagestructure.

[Explanation of Description Manner, Basic Terms, and Usage in thePresent Application]

1. In the present application, a description in the embodiments may bemade after divided in plural sections if necessary for convenience'ssake. These plural sections are not independent each other, but they mayeach be a part of a single example or one of them may be a partialdetail of the other or a modification example of a part or whole of theother one unless otherwise specifically indicated. In principle,description on a portion similar to that described before is notrepeated. Moreover, when a reference is made to constituent elements inthe embodiments, they are not essential unless otherwise specificallyindicated, limited to the number theoretically, or principally apparentfrom the context that it is not.

Further, the term “semiconductor device” as used herein means mainly asimple device such as various transistors (active elements) or a deviceobtained by integrating such a simple device as a main element with aresistor, a capacitor, and the like over a semiconductor chip or thelike (for example, a single-crystal silicon substrate). It should benoted that a simple device is obtained by integrating a plurality ofminute elements. Typical examples of the various transistors includeMISFET (metal insulator semiconductor field effect transistor) typifiedby MOSFET (metal oxide semiconductor field effect transistor) and IGBT(insulated gate bipolar transistor). Further, even in the “MOS”, aninsulating film is not limited to that made of an oxide.

2. Similarly, with regard to any material, any composition or the likein the description of the embodiments, the term “X made of A” or thelike does not exclude X having, as one of the main constituentcomponents thereof, an element other than A unless otherwisespecifically indicated or principally apparent from the context that itis not. For example, the term “X made of A” means that “X has A as amain component thereof”. It is needless to say that, for example, theterm “silicon member” is not limited to a member made of pure siliconbut also means a member made of an SiGe alloy or another multi-elementalloy having silicon as a main component or a member containing anadditive in addition. Similarly, the term “silicon oxide film”, “siliconoxide-based insulating film”, or the like is not limited to a relativelypure undoped silicon oxide (undoped silicon dioxide) but needless tosay, it embraces FSG (fluorosilicate glass) film, TEOS-based siliconeoxide film, SiOC (silicon oxycarbide) film, or carbon-doped siliconoxide film, a thermal oxidation film such as OSG (organosilicate glass)film, PSG (phosphorus silicate glass) film, or BPSG (borophosphosilicateglass) film, a CVD oxide film, silicon oxide films obtained by themethod of application such as SOG (spin on glass) and nano-clusteringsilica (NSC) film, silica-based low-k insulating films (porousinsulating films) obtained by introducing pores into members similar tothem, and composite films with another silicon-based insulating filmwhich films contain any one of the above-mentioned films as a principalconstituent element.

In addition, silicon-based insulating films ordinarily used in thesemiconductor field like silicon oxide based insulating films aresilicon nitride based insulating films. Materials which belong to such agroup include SiN, SiCN, SiNH, and SiCNH.

3. Preferred examples of the shape, position, attribute, and the likewill be shown below, however, it is needless to say that the shape,position, attribute, and the like are not strictly limited to thesepreferred examples unless otherwise specifically indicated or apparentfrom the context that it is not.

4. When a reference is made to a specific number or amount, the numberor amount may be greater than or less than the specific number or amountunless otherwise specifically indicated, limited to the specific numberor amount theoretically, or apparent from the context that it is not.

5. The term “wafer” usually means a single crystal silicon wafer overwhich a semiconductor device (which may be a semiconductor integratedcircuit device or an electronic device) is to be formed. It is howeverneedless to say that it embraces a composite wafer of a semiconductorlayer and an insulating substrate such as epitaxial wafer, SOIsubstrate, or LCD glass substrate.

6. “Ionization sputtering” is one of directive sputtering methods.Compared with typical metal sputtering film formation that dependsmainly on electrically neutral sputtering atoms or molecules, orclusters thereof, it realizes sputtering film formation with goodcoverage by making use of the property of ionized metal ions incident tothe wafer surface with a relatively large perpendicular velocitycomponent when a sheath voltage is applied (a bias may be appliedadditionally). Ionization sputtering has various systems. A PCM systemwill hereinafter be described specifically, but it is needless to saythat the ionization sputtering system in the invention is not limited toit. Accordingly, the system is not limited to “ionization sputtering”insofar as ionized metal atoms for film formation substantiallycontribute to film formation. In this embodiment, a specific descriptionis made using, as an ionization sputtering apparatus, “I-1080 PCM”(trade name; product of Canon Anelva) employing the PCM system, but anSIP-PVD (self-ionized plasma physical vapor deposition) apparatus ofApplied Materials can also be used as an ionization sputteringapparatus. ULVAC Incorporation also provides an analogous apparatus.

[Details of embodiment] Embodiments will be described in further detail.In all the drawings, the same or like members will be identified by thesame or like symbols or reference numerals and overlapping descriptionswill be omitted in principle.

In the accompanying drawings, hatching or the like is sometimes omittedeven from the cross-section when it makes the drawing cumbersome andcomplicated or when a member can be discriminated clearly from a void.In this context, when apparent from the explanation or the like, acontour of the background is sometimes omitted even if a hole is closedwhen viewed from the top. Furthermore, hatching may be given to aportion other than a cross-section in order to clearly show that it isnot a void.

The detailed description on the formation technology of analuminum-based metal electrode by using PCM sputtering film formationcan be found in Japanese Patent Application No. 2009-092973 (Filed onApr. 7, 2009 in Japan) so that the description on it is not repeatedherein in principle.

1. Explanation About a Metal Film Forming Apparatus and the Like to beUsed in the Manufacturing Method of a Semiconductor Device According toOne Embodiment of the Present Application (Mainly, FIGS. 1 and 2)

First, a metal film forming apparatus and the like to be used in themanufacturing method of a semiconductor device according to the oneembodiment of the present application will be described briefly. FIG. 1is a plan view illustrating the configuration of a multi-chamber type(cluster type) wafer processing apparatus to be used in themanufacturing method of a semiconductor device according to the oneembodiment of the present application.

As illustrated in FIG. 1, sputtering apparatuses (a PCM ionizationsputtering film forming chamber 58 for TiW, an AlSi sputtering chamber61, and a long throw sputtering film forming chamber 59 for TiW), a heattreatment apparatus (a pre-heat treatment chamber 56), an etchingapparatus (a sputter etching chamber 57) to be used in theabove-described manufacturing process are integrated in a clusterapparatus 51. This cluster apparatus 51 has a load port 52 (or ananterior chamber) for housing therein four wafer cassettes 53 at normalpressure. A wafer housed in the load port 52 is supplied to eachprocessing chamber after passing through either one of the two load lockchambers 54 and then through a vacuum transfer chamber 55 having aninside converted into vacuum. When the wafer is discharged from theprocessing chamber, it is discharged in reverse order.

In an example shown in this embodiment, a silicidation annealing stepafter formation of a TiW film is performed by using a batch processingfurnace not in but outside the multi-chamber type wafer processingapparatus 51. This step may be performed without bringing the wafer 1into contact with the atmosphere in a series of processes by employing asingle-wafer type RTA (rapid thermal annealing) chamber as one of aplurality of AlSi sputtering chambers 61.

FIG. 2 is a schematic cross-sectional view of a PCM (point cuspmagnetron) system sputtering chamber 58 to be used in a step of forminga tungsten-based barrier metal film in the manufacturing method of asemiconductor device according to the one embodiment of the presentapplication. This sputtering chamber (sputtering apparatus) is, similarto general-purpose metal sputtering apparatuses, embraced in a magnetronsputtering system. As illustrated in FIG. 2, a lower electrode (waferstage) 62 is placed in the lower portion of the chamber 58 and at thetime of film formation, the wafer 1 is set on a wafer stage 62 with adevice surface 1 a (surface opposite to a back surface 1 b) up. To thelower electrode 62, a high frequency bias (second high-frequency power)can be applied from a lower electrode high frequency bias supply 63 (forexample, 13.56 MHz). It can also be grounded directly. The wafer stage62 has therein an electrostatic chuck electrode 65 and it can be turnedON or OFF by using an electrostatic chuck control system 64.

In the upper part of the chamber 58, an upper electrode (target backingplate) 66 is placed opposite to the wafer stage 62 and it has, on thelower surface thereof, a tungsten-based target 67 (as the target, forexample, a TiW target containing about 10% of titanium is used). To theupper electrode 66, a DC power (DC bias) and a high frequency power(first high-frequency power) can be applied from an upper electrode DCbias supply 74 and an upper electrode high-frequency supply 75 (forexample, 60 MHz) (either or both can be applied). This enables, forexample, excitation of an argon plasma 76 or the like and generation ofa desired bias voltage (in an ionization sputtering mode, at least thisfirst high frequency power is ON). A magnet holding rotary table 68 inwhich an S pole 71 and an N pole 72 are arranged alternately is placedin the vicinity of the upper side of the target backing plate 66 and itis rotatable using a drive shaft 73 (rotating shaft).

The chamber 58 has, outside thereof, a gas supply control system 77, bywhich a gas such as an argon gas can be supplied to the chamber 61through a gas supply channel 78. In addition, the chamber 58 is vacuumevacuated using a vacuum evacuation system 79 via an exhaust port 81located in the lower portion of the chamber 58, making it possible tokeep high vacuum necessary for sputtering.

2. Explanation About One Example of the Device Structure of a PowerMOSFET Manufactured by the Manufacturing Method of a SemiconductorDevice According to the One Embodiment of the Present Application (Basedon Mainly FIGS. 3, 6, and 17)

FIG. 3 is a top view of a device illustrating one example of a powerMOSFET manufactured by the manufacturing method of a semiconductordevice according to the one embodiment of the present application. Asillustrated in FIG. 3, in a power MOSFET device chip 8 having an elementon a square or rectangular plate-like silicon-based semiconductorsubstrate (which is a wafer before dicing into individual chips), asource pad region 11 (aluminum-based pad) at the center portion occupiesa major area of the chip. The chip has therebelow a band-like repeateddevice pattern region R (linear cell region) in which many band-likegate electrodes and band-like source contact regions have been formedalternately with band-like SBD regions 10 therebetween. More correctly,the linear cell region R extends below almost the entirety of the sourcepad region 11 and a portion surrounded with a broken line is a part ofthe linear cell region. This linear cell region R has, at the peripherythereof, a gate pad region 13 for extracting a gate electrode from theperiphery to the outside. The linear cell has, at the further peripherythereof, an aluminum guard ring 19. The chip has, at the outermostperipheral portion thereof, a region to be divided by dicing or thelike, that is, a scribe region 14.

FIG. 16 is an extended cross-sectional structure view of the devicecorresponding to FIG. 14. FIG. 17 is an equivalent circuit diagram ofthe device corresponding to FIG. 16. Based on them, the cross-section ofthe device corresponding to the SBD portion and the band-like repeateddevice pattern region cutout portion R illustrated in FIG. 3 will beoutlined.

As illustrated in FIG. 17, the power MOSFET device incorporates thereinan SBD as a protection diode for allowing a surge voltage to escape. Thecross-section (SBD portion and band-like repeated device pattern regioncutout portion R) of the manufacturing step (upon completion of theformation of an aluminum-based source electrode) is as illustrated inFIG. 16. Described specifically, a device is formed over a silicon-basedsemiconductor single-crystal wafer 1 (surface side 1 a and back side 1b). As the wafer 1, for example, that having an n+ silicon substrateportion 1 s, an n-epitaxial layer 1 e (most of this portion forms ann-type drift region 2), and the like is used. The n+ silicon substrateportion 1 s has, on the back side thereof, a back-side metal layerserving as a drain electrode 20.

As illustrated in FIG. 16, the SBD region 10 lies at the center portionand it has a cell region 12 of MOSFET on both sides thereof. In an SBDmain portion 10 a of the SBD region 10, an n-epitaxial layer 1 e and alower-layer barrier metal film (first layer film) 23 a face each otherwith a thin titanium silicide film (not illustrated) therebetween andform a Schottky junction. On both sides of the n-epitaxial layer 1 ebelow the SBD main portion 10 a, relatively deep p-well regions 15 areprovided and it configures an element isolation region together withdummy trench gate electrodes 6 d.

On the other hand, the n-epitaxial layer 1 e of the cell region 12 ofMOSFET has, in the upper portion thereof, a p-base region 3 and a trenchgate electrode (polysilicon electrode) 6 penetrating through this p-baseregion 3 and reaching the inside of the n-epitaxial layer 1 e. Thistrench gate electrode 6 is isolated from a semiconductor regiontherearound via a gate insulating film 7. In the surface region of thep-base regions 3 on both sides of the trench gate electrode 6, n+ sourceregions 4 are provided. A p+ body contact region 5 is provided in thesurface of the semiconductor region between the n+ source regions 4adjacent to each other. The top portion of the trench gate electrode 6is covered with a relatively thick interlayer insulating film 21 and arecess (source contact trench) 22 having a two-stage structure is formedbetween the interlayer insulating films 21 adjacent to each other. Sucha structure has the merit of increasing the area of a contact portionand thereby improving the contact characteristics. On the other hand,the recess (source contact trench) 22 having a two-stage structure hasthe demerit of complicating the structure at the boundary between thebottom stage (recess bottom lower-stage 26) and the upper stage (recessbottom upper-stage 25) (refer to FIG. 11). Accordingly, it is alsopossible to form a structure having a flat bottom in order to avoid sucha demerit.

A lower-layer barrier metal film (first layer film) 23 a and anupper-layer barrier metal film (second layer film) 23 b are formed so asto cover the surface on the surface side of the semiconductor substrate1 and the interlayer insulating film 21. A thick aluminum-based metalfilm (source electrode) 24 is formed over the upper-layer barrier metalfilm.

3. Explanation About the Outline of a Device Cross-Sectional FlowDiagram Relating to the Manufacturing Method of a Semiconductor DeviceAccording to the One Embodiment of the Present Application (Based onMainly FIGS. 4 to 14)

With a 0.15-μm process linear trench gate power MOSFET as an example,the process flow will next be described using the cross-section of thedevice corresponding to the trench gate cell portion 12 of the band-likerepeated device pattern region cutout portion R explained in Section 2based on FIG. 3.

FIG. 4 is a device cross-sectional flow diagram (a step of forming aresist pattern for the formation of a source contact trench) at thetrench gate cell portion in the manufacturing method of a semiconductordevice according to the one embodiment of the present application. Inthis section, explained is an example of using, as a raw material wafer,an n-epitaxial wafer 1 obtained by forming an n-epitaxial layer (forexample, having a thickness of about 4 μm) on a 200Ø n+ type siliconsingle crystal wafer (silicon-based wafer). The diameter of the wafer isnot limited and it may be 3000 or 4500. A wafer having a conductivitytype of p can also be used. Further, the wafer is not limited to anepitaxial wafer but may be another semiconductor substrate, aninsulating substrate or the like. If necessary, the wafer may be asemiconductor wafer or a substrate, each comprised of a material otherthan silicon.

As illustrated in FIG. 4, the semiconductor wafer 1 is comprised mainlyof an n+ silicon substrate portion 1 s and an epitaxial layer 1 e. Theepitaxial layer 1 e has therein an n-drift region 2 which is originallyan n-epitaxial layer and has thereover a p-channel region (p-baseregion) 3, an n+ source region 4, and the like. A plurality of trenchgate electrodes (polysilicon electrodes) 6 are provided at certainintervals in such a manner that the upper portion thereof protrudes fromthe epitaxial layer 1 e. Each of the trench gate electrodes 6 has,around the middle and lower portions thereof, a gate insulating film 7.The semiconductor wafer 1 has, on the device surface side 1 a thereof,an interlayer insulating film 21 and it completely covers therewith eachof the trench gate electrodes 6. Examples of this interlayer insulatingfilm 21 include a multilayer insulating film comprised of, in the orderstarting from the lower layer, a silicon nitride film (siliconnitride-based insulating film) having a thickness of about 60 nm, a PSGfilm (silicon oxide-based insulating film) having a thickness of about300 nm, and an SOG film (silicon oxide-based insulating film) having athickness of about 95 nm.

The interlayer insulating film 21 has thereover a resist film 9 forprocessing. When dry etching is performed with this resist film 9 as anetching mask, a recess (source contact trench) 22 is formed asillustrated in FIG. 5. The state after removal of the resist film 8which becomes unnecessary is illustrated in FIG. 6.

When dry etching is then performed further with the patterned interlayerinsulating film 21 as an etching mask, the recess (source contacttrench) 22 is extended to the upper end of the p-channel region 3 asillustrated in FIG. 7.

FIG. 8 is the upper surface of the device (upper surface of the wafer)corresponding to FIG. 7 (corresponding also to FIG. 9) at this time.FIG. 9 also illustrates a region corresponding to the cell repeatingunit region G in FIG. 8.

Following FIG. 7, a p+ body contact region 5 is introduced into thesurface region of the p-channel region 3 by ion implantation through thesource contact trench 22 (having, for example, a bottom width of about300 nm, a depth of about 850 nm, and an aspect ratio of 2 or greater butnot greater than 5 and about 2.8 on average).

Then, as illustrated in FIG. 11, the surface side 1 a of the wafer 1 issubjected to isotropic oxide-film etching to reduce the width of theinterlayer insulating film 21, resulting in completion of the formationof a recess (source contact trench) 22 having a two-stage structurecomprised of a recess bottom upper-stage 25 and a recess bottomlower-stage 26. The upper surface of the device (upper surface of thewafer) corresponding to FIG. 11 at this time is shown in FIG. 10.

After the device as illustrated in FIG. 11 is obtained, a TiW film isformed as a lower-layer barrier metal film 23 a over almost the wholesurface of the semiconductor wafer 1 on the device surface side 1 a asillustrated in FIG. 12 by PCM sputtering film formation (ionizationsputtering film formation) while applying a bias to the wafer side.

The sputtering film formation of the TiW film 23 a is performed, forexample, in the following procedure. Described specifically, the wafer 1is housed in the wafer transport container (wafer cassette) 53illustrated in FIG. 1 and the cassette is set in the load port 52 of themulti-chamber type wafer processing apparatus 51. First, the wafer 1 isset on a wafer stage in a degassing chamber 56 and is subjected topreheat treatment for removing moisture or the like from the surface.The preheat treatment is performed, for example, under the followingconditions: a stage temperature set at about 375° C., pressure at about266 Pascal, an argon flow rate at about 200 sccm, and treatment time forabout 50 sec.

The wafer 1 is then set on a wafer stage of the sputter etching chamber57 illustrated in FIG. 1 and is subjected to sputter etching forremoving the oxide film from the surface. The sputter etching isperformed, for example, under the following conditions: an uncontrolledstage temperature, a pressure at about 0.5 Pascal, and an argon flowrate at about 37.5 sccm. Plasma excitation is performed using, forexample, a CCP (capacitively coupled plasma) system under the followingconditions: a high-frequency power at 400 W (for example, 60 MHz),etching time for about 25 seconds, and an etching amount of about 10 nm.

The resulting wafer 1 is then set on a wafer stage of the PCM ionizationsputtering film forming chamber 58 for TiW illustrated in FIGS. 1 and 2and lower-layer TiW sputtering film formation treatment is performed,for example, in accordance with the PCM sputtering system. The film isformed, for example, under the following conditions: film thickness ofabout 125 nm, treatment time for about 50 sec, degree of vacuum at about18 Pascal, an argon flow rate at about 175 sccm, stage temperature atroom temperature (wafer is, for example, gas cooled with anelectrostatic chuck ON), target-side high frequency power at about 4 kW(for example, 60 MHz), wafer-side high-frequency power at about 400 W(for example, 13.56 MHz), target-side DC bias voltage OFF (when the filmformation rate is insufficient, application of the voltage increases thefilm formation rate), and a target composition having 10% titanium and90% tungsten (each, wt. %). This step may be performed by not only thePCM system but also another ionization sputtering system.

Then, as illustrated in FIG. 13, an upper-layer barrier metal film 23 b(TiW film) is formed over almost the whole surface of the TiW film 23 aby PCM sputtering film formation without substantially applying a biasto the wafer side. This PCM sputtering film formation (ionizationsputtering film formation) of the titanium nitride film 23 b withoutsubstantially applying a bias to the wafer side is performed, forexample, in the following procedure. Described specifically, the lowerelectrode 62 is grounded directly in the PCM ionization sputtering filmforming chamber 58 for TiW (FIG. 2) illustrated in FIG. 1 and the wafer1 is subjected to PCM sputtering film formation treatment to form theTiW film 23 b. The film is formed, for example, under the followingconditions: film thickness of about 125 nm, treatment time for about 50seconds, degree of vacuum at about 18 Pascal, an argon flow rate atabout 175 sccm, a stage temperature at room temperature (the wafer isgas cooled with an electrostatic chuck ON), a target-side high-frequencypower at about 4 kW, a wafer-side high-frequency power OFF, atarget-side DC bias voltage OFF (when the film formation rate isinsufficient, application of the voltage increases the rate), and atarget composition having 10% titanium and 90% tungsten (wt. %). Thisstep can be performed by not only the PCM system but also anotherionization sputtering system. This step can also be performed by using asputtering film forming chamber not employing a typical ionizationsputtering system such as LT (long throw) sputtering film formingchamber 59 for TiW illustrated in FIG. 1, depending on the shape of therecess (source contact trench) 22 (for example, when a requirement forthe filling property is relatively loose).

When silicidation annealing is then performed, the surface of a siliconmember contiguous to the portion of the TiW film 23 a in FIG. 13 becomesa thin titanium silicide film with titanium supplied from the lowersurface and inside of the TiW film 23 a. Since illustration of such achange makes the view more complicated, it is omitted from FIGS. 13 to16.

The silicidation annealing is performed, for example, in the followingprocedure. Described specifically, the wafer 1 is transferred outside ofthe multi-chamber type wafer processing apparatus illustrated in FIG. 1.It is housed in the wafer cassette 53, transferred to, for example, abatch system annealing apparatus, and subjected to silicidationannealing. The silicidation annealing is performed, for example, underthe following conditions: a temperature at about 650° C., an atmosphericpressure, for example, at normal pressure, a nitrogen gas flow rate ofabout 15 liter/min, and annealing time for about 10 seconds. This stepcan also be performed in the multi-chamber type wafer processingapparatus 51 or by using a single-wafer type RTA apparatus placed inanother place.

After completion of the silicidation annealing, a seed aluminum-basedmetal film 24 s is formed over almost the whole surface of the TiW film23 b as illustrated in FIG. 14, for example, by PCM sputtering filmformation (in, for example, the aluminum-based metal film sputteringchamber 61 illustrated in FIG. 1 made similar to the PCM ionizationsputtering film forming chamber 58 for TiW illustrated in FIG. 2). Theseed aluminum-based metal film 24 s and the main aluminum-based metalfilm 24 can also be formed by using another ionization sputtering filmformation apparatus. When the requirement for the filling property isnot severe, a typical non-ionization sputtering film formation apparatussimilar to the LT sputtering film forming chamber 59 (FIG. 1) can alsobe used.

The sputtering film formation of the seed aluminum-based metal film 24 sis performed, for example, in the following procedure. Describedspecifically, the wafer 1 is discharged from the batch-type annealingapparatus, housed in the wafer transfer container (wafer cassette) 53illustrated in FIG. 1, and set in the load port 52 of the multi-chambertype wafer processing apparatus 51. The wafer 1 is set again on thewafer stage in the degassing chamber 56 and preheated for removingmoisture or the like from the surface. Preheating is performed, forexample, under the following conditions: a stage temperature set atabout 375° C., a pressure at about 266 Pascal, an argon flow rate atabout 200 sccm, and pre-heating time for about 50 sec.

The wafer 1 is then set on the wafer stage 62 in the aluminum-basedmetal film sputtering chamber 61 illustrated in FIGS. 1 and 2 and theseed aluminum-based metal film 24 s is formed by sputtering. Formationof the seed aluminum-based metal film is performed, for example, underthe following conditions: a stage temperature set at about 420° C. (withthe electrostatic chuck OFF), a pressure at about 5 Pascal, an argonflow rate at about 20 sccm, an upper electrode high-frequency power at 4kW (for example, 60 MHz), an upper electrode DC power at 1 kW, a lowerelectrode high-frequency power at 200 W (for example, 13.56 MHz), asputtering time for about 3 minutes, and a film formation amount ofabout 600 nm. The preset temperature of the stage is preferably fromabout 400° C. to 440° C. Since the electrostatic chuck is OFF, it ispossible to prevent closure of the upper portion of the source contacttrench 22 which will otherwise occur as a result of an excessive rise inthe wafer temperature and an excessive progress of reflow of thedeposited aluminum-based metal member at the time of forming the seedaluminum-based metal film. This means that in the former half period ofthe formation of a film using the aluminum-based metal member, formationof an adequately thick aluminum-based metal member film on the bottomsurface portion of the source contact trench 22 greatly contributes tothe final filling property rather than flattening by reflow.Accordingly, application of the bias to the lower electrode isparticularly effective in the former half period because it enablespushing of metal ions onto the wafer more perpendicularly.

As illustrated in FIG. 14, an aluminum-based metal film 24 is formedover almost the whole surface of the seed aluminum-based metal film 24 sby PCM sputtering film formation (in, for example, the aluminum-basedmetal film sputtering chamber 61 illustrated in FIG. 1 made similar tothe PCM ionization sputtering film forming chamber 58 for TiWillustrated in FIG. 2)) to, together with the seed aluminum-based metalfilm 24 s, fill the inside of the recess (source contact trench) 22 andfurther to cover the upper portion of the titanium nitride film 23 boutside the recess (source contact trench) 22.

The latter sputtering (latter half of the sputter film formation) forforming the aluminum-based metal film 24 is performed, for example, inthe following procedure. Described specifically, the former sputteringconditions are changed continuously to the latter sputtering conditionswithout moving the wafer 1 from the wafer stage 62 in the film formingchamber 61 upon formation of the seed aluminum-based metal film 24 s(under almost similar conditions). The latter sputtering film formationfor forming the aluminum-based metal film 24 is performed under thefollowing conditions: a stage temperature set at about 420° C. (with anelectrostatic chuck ON), a pressure at about 5 Pascal, an argon flowrate at about 20 sccm, an upper electrode high-frequency power of 4 kW(for example, 60 MHz), an upper electrode DC power of 1 kW, a lowerelectrode high-frequency power OFF, a sputtering time for about 3minutes, and a film formation amount of about 600 nm. The stagetemperature is set preferably in a range of from about 400° C. to 440°C.

When the stage temperature upon sputtering film formation (in the formerhalf and the latter half) is set at less than 400° C., reflow does notproceed adequately, while when the stage temperature exceeds 440° C., anaggregation phenomenon of an undesired metal is likely to occur. In thesputtering formation (in the latter half), when the lower electrodehigh-frequency power is made ON, a similar aggregation phenomenon tendsto occur due to an undesired rise in the wafer temperature. As thesource electrode material, AlCu, pure Al, copper-based metal member andthe like as well as silicon-added aluminum-based metal (AlSi) areusable.

Then, the aluminum-based metal film 24 is patterned. A final passivationinsulating film (for example, an organic insulating film such as apolyimide resin film obtained by the method of application and having athickness of about 2 μm) is then formed over the patterned film,followed by formation of necessary openings. The resulting wafer isdiced into individual chips to obtain a device as illustrated in FIG. 3.

4. Explanation About the Barrier Metal Structure of a DeviceManufactured Using a Manufacturing Method of a Semiconductor DeviceAccording to Another Embodiment of the Present Application (Mainly FIG.15)

The structure explained herein is a device structure obtained accordingto a modification example of the two-stage barrier metal film formationprocess explained referring to FIGS. 12 and 13.

FIG. 15 is a device cross-sectional flow diagram (a step of forming abarrier metal film) at a trench gate cell portion in a manufacturingmethod of a semiconductor device according to another embodiment of thepresent application. In this process, a tungsten-based barrier metalfilm 23 (TiW film) is formed over the whole thickness by carrying outionization sputtering film formation such as PCM sputtering filmformation while applying a bias to the wafer side.

The film is formed, for example, under the following conditions: a filmthickness of about 250 nm, a sputtering time for about 100 seconds, adegree of vacuum at about 18 Pascal, an argon flow rate at about 175sccm, a temperature of the stage at room temperature (for example, thewafer is gas cooled with an electrostatic chuck ON), a target-sidehigh-frequency power at about 4000 W (for example, 60 MHz), a wafer-sidehigh-frequency power at about 400 W (for example, 13.56 MHz), atarget-side DC bias voltage OFF (when the film formation rate isinsufficient, application of a bias improves the rate), and a targetcomposition having 10% titanium and 90% tungsten (wt. %).

This one-stage barrier metal film formation process enables to decreasethe whole film thickness because the entirety of the tungsten-basedbarrier metal film 23 (TiW film) thus obtained is in an amorphous formwith a good barrier property.

On the other hand, according to the two-stage barrier metal filmformation process explained in Section 3, the lower-layer barrier metalfilm (first layer film) 23 a is in an amorphous form with a good barrierproperty so that it acts as a good barrier against diffusion ofaluminum. The upper-layer barrier metal film (second layer film) 23 b,on the other hand, is in the form of a columnar grain with inferiorbarrier property, but a conventionally proven good reflow property of itto aluminum can be utilized advantageously.

5. Explanation on the Data Showing the Cross-Sectional Shape of thePower MOSFET Manufactured Using the Manufacturing Method of aSemiconductor Device According to the One Embodiment of the PresentApplication and Conclusion on the Present Application as a Whole (MainlyFIG. 18)

FIG. 18 is an SEM (scanning electron microscope) photographcorresponding to FIG. 13, more specifically, a cross-sectional shape ofthe cell region (trench gate cell portion) 12 of the power MOSFETmanufactured using the two-stage barrier metal film formation processexplained in Section 3. From the drawing, it is apparent that the trenchbottom portion B, which is the bottom portion of the recess (sourcecontact trench) having a two-stage structure, is almost completelyfilled. Comparison between the upper-layer barrier metal 23 b and thelower-layer barrier metal film 23 a over the interlayer insulating film21 (FIG. 13) suggests that the grain of the upper-layer barrier metal 23b is in the column form.

According to the analysis by the present inventors, deterioration in thebarrier property is presumed to occur because a space is likely toappear at the boundary among columnar grains (columnar crystals) atportions where the background is outwardly convex. It is presumed thatin the barrier metal film in the amorphous form, the boundary of thegrains does not act as a high-speed diffusion path so that such abarrier metal film exhibits a good barrier property. No such problem dueto columnar grains occurs in a titanium-based barrier metal (TiN or thelike) comprised mainly of titanium because it has a dense structure. Adevice incorporating an SBD should use a tungsten-based barrier metal inorder to secure the properties of the SBD and in addition, the devicecan be manufactured more easily when a tungsten-based barrier metal isused than when a titanium-based barrier metal, from the standpoint ofthe warpage of the wafer or the like.

In ionization sputtering film formation, application of a bias power tothe wafer side provides a film in an amorphous form, because the grainstructure is converted to the amorphous structure due to a high energyof incident metal particles. In addition, application of a bias power tothe wafer side causes re-sputtering on the bottom of the recess (sourcecontact trench) 22 and re-deposition onto the side surface of the bottomimproves the flattening processing.

Data analysis by the present inventors has revealed that in theformation of a barrier metal film by using various methods described inSections 3 and 4, warpage of the wafer is reduced compared with thewafer manufactured using the conventional non-ionization sputtering filmformation (for example, typical long throw sputtering). Describedspecifically, when an average warpage amount is compared immediatelyafter silicidation annealing, that of a wafer obtained usingnon-ionization sputtering film formation is about 68.26 μm, while thatof a wafer obtained using the two-stage system described in Section 3 isabout 39.56 μm.

6. Summary

The invention made by the present inventors was described specificallybased on some embodiments. The present invention is not limited to them.It is needless to say that it can be modified without departing from thescope of the invention.

For example, in the above-described embodiments, the invention wasspecifically described using a power MOSFET as an example. It isneedless to say that the invention is not limited to it but it can beapplied widely not only to simple elements such as IGBT but alsointegrated circuit devices including them.

In the above-described embodiments, N-channel type devices such asN-channel type power MOSFET were described specifically. It is needlessto say that the present invention is not limited to them but can beapplied to P-channel type devices such as P-channel type power MOSFET.In this case, it is only necessary to carry out a PN reversing operationfor completely interchanging P and N.

In the above-described embodiment, a sputtering film formation methodwas described mainly as the formation method of a metal member film. Itis needless to say that the invention is not limited to it and a filmformation method such as CVD or plating can be employed as needed.

1. A manufacturing method of a semiconductor device comprising the stepsof: (a) forming a recess downwards from the upper surface of a firstinsulating film over a first main surface of a semiconductor wafer; (b)forming a tungsten-based barrier metal film on the inner surface of therecess and the upper surface of the first insulating film by ionizationsputtering film formation while applying a bias voltage to thesemiconductor wafer; and (c) after the step (b), forming analuminum-based metal layer to cover therewith the tungsten-based barriermetal film over the inner surface of the recess and the upper surface ofthe first insulating film.
 2. The manufacturing method of asemiconductor device according to claim 1, wherein in the step (b), thetungsten-based barrier metal film contains tungsten as a main componentthereof and titanium as a secondary component.
 3. The manufacturingmethod of a semiconductor device according to claim 1, wherein thetungsten-based barrier metal film has a layer having mainly an amorphousstructure.
 4. The manufacturing method of a semiconductor deviceaccording to claim 1, wherein the semiconductor wafer has, over thefirst main surface thereof, a number of semiconductor chip regions and aSchottky barrier diode is formed in each of the chip regions.
 5. Themanufacturing method of a semiconductor device according to claim 4,wherein a power MOSFET is formed in each of the chip regions.
 6. Themanufacturing method of a semiconductor device according to claim 1,wherein the recess has a two-stage structure.